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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:08:59 03/31/2012 
-- Design Name: 
-- Module Name:    TestingBR - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TestingBR is
port( 
	 clka_tu : IN STD_LOGIC;
	 ena_tu : IN STD_LOGIC;
    wea_tu : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addra_tu : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
    dina_tu : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    clkb_tu : IN STD_LOGIC;
    enb_tu : IN STD_LOGIC;
    addrb_tu : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
    doutb_tu : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end TestingBR;

architecture Behavioral of TestingBR is

	component BR_CENTRALI_REFERENCE
	 PORT (
    clka : IN STD_LOGIC;
    ena : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    clkb : IN STD_LOGIC;
    enb : IN STD_LOGIC;
    addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
	end component;
	
	
begin

BR_CENTRALI_REFERENCE_1 : BR_CENTRALI_REFERENCE
			port map(
				clka => clka_tu,
				ena => ena_tu,
				wea => wea_tu,
				addra => addra_tu,
				dina => dina_tu,
				clkb => clkb_tu,
				enb => enb_tu,
				addrb => addrb_tu,
				doutb => doutb_tu
			);


end Behavioral;

